In conventional single-bit-per-cell memory systems (binary memory systems), each memory cell assumes one of two information storage states: either an "on" state or an "off" state. The state of each cell ("on" or "off") defines one binary bit of information. As a result, a binary memory system capable of storing N bits of binary data requires N separate memory cells.
Increasing the number of bits which can be stored using a binary memory system depends upon increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored. Methods for increasing the number of memory bits stored in a binary memory system have relied upon techniques such as manufacturing larger dies which contain more memory cells, or using improved photolithography techniques to build smaller memory cells. Reducing the size of a memory cell allows more cells to be placed on a given area of a single die.
An alternative to a binary memory system (which stores one binary bit per memory cell) is a multistate memory device which stores two or more binary bits of data in a single memory cell.
One type of memory device includes an array of electrically erasable and programmable devices known as flash memory cells. Each of such cells can be operated either as a binary memory device (storing one binary bit) or as a multistate memory device. To program a flash memory cell, appropriate voltages are applied to the source, drain, and control gate of the transistor which comprises the cell for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the cell to conduct a particular level of current between the source and drain. This voltage is termed the threshold voltage, V.sub.th, of the cell.
When a flash memory cell is operated as a binary memory device, the cell is programmed or erased to have a selected one of two different threshold voltages (the cell is either erased so as to have a first threshold voltage or it is programmed so as to have a second threshold voltage). The cell is then read by measuring whether the current between its source and drain (or a voltage related to such current) exceeds a threshold amount (for a known set of voltages applied to its source, control gate, and drain). Measurement of current having at least a first magnitude (a "first" current) between the source and drain regions determines an "on" or erased state of the cell (corresponding to a logic value of one). An "off" or programmed state of the cell (corresponding to a logic value of zero) is determined by a measured current less than the first current between the source and drain regions. For a given threshold voltage of a cell, the cell can be made to conduct or not conduct current (i.e., current greater than or equal to the first current) by applying a given set of voltages thereto. The cell conducts when a voltage applied to its control gate (with reference to its source voltage) is greater than the threshold voltage. By measuring whether a cell conducts current (i.e., current greater than or equal to the first current) at a given set of applied voltages, the state of the cell (programmed or if erased) is measured. Typically, such a measurement is made using a sense amplifier (as described below).
When a flash memory cell is operated as a multistate memory device, the cell is programmed or erased to cause it to have a selected one of three or more different threshold voltages. In other words, the cell is either erased (so as to have a first threshold voltage), or it is programmed into one of at least two programmed states (so as to have a second threshold voltage in one programmed state, or a third threshold voltage in another programmed state, or a fourth threshold voltage in a third one of the programmed states, and so on). Each distinct threshold voltage corresponds to a set of at least two binary data bits in the following sense. Application of a voltage less than a first threshold voltage to the cell's control gate causes conduction of less than a first current between the source and drain regions (corresponding to a first set of binary bits, e.g., "00" or "000"), application of a voltage greater than the first threshold voltage but less than a second threshold voltage to the cell's control gate causes conduction of more than the first current but less than a second current between the source and drain regions (corresponding to a second set of binary bits, e.g., "01" or "001"), application of a voltage greater than the second threshold voltage but less than a third threshold voltage to the cell's control gate causes conduction of more than the second current but less than a third current between the source and drain (corresponding to a third set of binary bits, e.g., "10" or "010"), application of a voltage greater than the third threshold voltage to the cell's control gate causes conduction of more than the third current between the source and drain (corresponding to a fourth set of binary bits, e.g., "11" or "011"), and so on. This effectively allows multiple bits of binary data to be stored within a single memory cell.
When reading the state of a memory cell (operated as a multistate memory device), a binary decoded value (an ordered set of two or more binary bits indicative of the data stored in the cell) is generated which corresponds to a measured current between the cell's source and drain (or a measured voltage related to such current). Typically, the voltage related to the source-to-drain current is measured using sense amplifier circuitry to which a set of preselected reference voltage values (each corresponding to one of the threshold voltages) are applied, in a manner to be explained with reference to FIG. 3 below.
Memory system 3 shown in FIG. 1 includes an array 16 of nonvolatile memory cells (which can be flash memory cells), and is an example of a memory system which can be operated as a multistate memory system. Memory system 3 is implemented as an integrated circuit. Memory cell array 16 comprises rows and columns of memory cells (each row of cells connected along a different wordline, and each column of cells connected along a different bitline). Memory chip 3 also includes row decoder circuit (X address decoder) 12 and column multiplexer circuit (Y multiplexer) 14 connected to array 16.
Wordlines of array 16 are conveniently referred to as being numbered consecutively from top to bottom of array 16, so that the wordlines are: wordline 0 (or "WL0"), wordline 1 (or "WL1"), wordline 2, wordline n-1, and wordline n (where n is an integer)
FIG. 2 is a schematic diagram of an implementation of memory array 16 of FIG. 1 from which data can be read in accordance with the present invention. The FIG. 2 implementation of array 16 includes flash memory cells arranged in rows and columns. Each cell is implemented by a floating-gate N-channel transistor (e.g., transistors N1, N3, and Nn connected along bitline 13), as shown schematically. All the cells in a particular column have their drain regions connected to a common bitline (e.g., bitline 13 or bitline 15) and all the cells in a particular row have their control gates connected to a common wordline (one of wordlines WL0, WL1, . . . , WLn). The source region (S) of each of the cells is connected to a common source line SL. Alternatively, it is possible to arrange the cells into array segments having separate source lines that can be sequentially accessed during an erase cycle (e.g., to reduce the maximum erase current). The drain region (D) of each cell is connected to the bitline associated with the column in which the cell is located. For example, cell N1 has its drain region connected to bitline 13.
The control gate of each of the cells is driven by a driver circuit (not shown in FIG. 2 but included within X decoder circuit 12 of FIG. 1) which asserts an appropriate control voltage to such control gate.
The sources of the cells held by circuit 16 at a selected source potential (which is usually ground potential for the chip during a read or programming operation).
With reference to FIG. 1, memory chip 3 also includes control engine (or "controller") 29, output buffer 20, input buffer 18, and input/output pin (or pins) 30. Each pin 30 can assert data from output buffer 20 (e.g., data read from array 16) to an external device (not shown), and can receive input data from the external device. Input buffer 18 receives input data from pin(s) 30 and asserts the data to controller 29 and to Y-multiplexer 14, which cause the data to be written to array 16.
Address buffers A0 through Ap receive address bits from the external device. Some of the address buffers are configured to send buffered address bits to row decoder circuit 12 in response to receiving address bits from the external device, and others of the address buffers are configured to send buffered address bits to column multiplexer circuit (Y multiplexer) 14 in response to receiving address bits from the external device.
Each of the cells of memory array 16 is indexed by a row index (an "X" index determined by decoder circuit 12) and a column index (a "Y" index determined by a Y decoder circuit within circuit 14). As described with reference to FIG. 2, each column of cells of array 16 comprises "n" memory cells (where n is an integer), with each cell implemented by a single floating-gate N-channel transistor. The drains of all transistors of a column are connected to a bitline, the control gate of each of the transistors is connected to a different wordline, and the sources of the transistors are held at a source potential (which is usually ground potential for the chip during a read or programming operation).
Each memory cell is a nonvolatile memory cell since the transistor of each cell has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of the N-channel transistors) depends on the amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating gate determines a data value that is stored "semipermanently" in the corresponding cell. Where each of the N-channel transistors is a flash memory device, the charge stored on the floating gate of each is erasable (and thus the data value stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source (in a well known manner). In memory systems comprising an array of non-volatile memory cells other than flash memory cells, such non-volatile cells are erased using other techniques which are well known.
Controller 29 of chip 3 controls detailed operations of chip 3 such as the various individual steps necessary for carrying out programming, reading, and erasing operations. Controller 29 thus functions to reduce the overhead required of the external processor (not depicted) typically used in association with chip 3. In response to a command or commands (e.g., a command received at pin 30 and asserted through buffer 18 to controller 29), controller 29 causes chip 3 to operate as a multistate memory system, and in response to another command (or another set of commands) controller 29 causes chip 3 to operate as a binary memory system.
In order to be operable as a multistate memory system, chip 3 must include a source or sources of appropriate voltages for programming each cell of array 16 to a selected one of at least two different programmed states and erasing each cell to an erased state distinct from the programmed states (or chip 3 must be coupled to an external source or sources of such voltages).
Chip 3 executes a write operation as follows. Appropriate ones of the address bits (Ao through Ap) are asserted to decoder circuit 12 and Y multiplexer circuit 14. In response to these address bits, circuit 12 determines a row address which selects one row of cells and circuit 14 determines a column address (which selects one column, or a number of columns, of memory cells of array 16). The row and column address thus together select one or more target cells in one selected row. In response to control signals (indicative of a write command) supplied from controller 29, a signal indicative of data present at the output of input buffer 18 is asserted through circuit 14 to the target cell or cells of array 16 determined by the row and column address (e.g., to the drain of each such cell). Depending on the value of each of the data bits, the corresponding target cell is either programmed (to one of at least two different programmed states when chip 3 operates as a multistate memory, or to a single programmed state when chip 3 operates as a binary memory) or it remains in an erased state.
Chip 3 executes a read operation as follows. Appropriate ones of the address bits (Ao through Ap) are asserted to decoder circuit 12 and Y multiplexer circuit 14. In response to these address bits, circuit 12 determines a row address which selects one row of cells and circuit 14 determines a column address (which selects one column, or a number of columns, of memory cells of array 16). The row and column address thus together select one or more target cells in one selected row. In response to control signals (indicative of a read command) supplied from control unit 29, a current signal (a "data signal") indicative of a data value stored in each target cell of array 16 is supplied from the drain of each target cell through the bitline of the target cell and then through circuit 14 to sense amplifier circuit 19. Typically, eight target cells (in a single row) are read simultaneously, and thus eight data signals are supplied in parallel to sense amplifier circuit 19 and eight output signals are asserted in parallel from circuit 19 to output buffer 20. Each data signal is processed in sense amplifier circuit 19 to generate one of the output signals, and each output signal is buffered in output buffer 20 and then asserted through pin(s) 30 to an external device. More generally, sense amplifier circuit 19 has L input lines and X output lines (where numbers L and X are explained below).
We next describe the manner in which sense amplifier circuit 19 processes a data signal from a selected target cell of array 16, with chip 3 operating as a binary memory system (i.e., with each cell of array 16 operating as a binary memory device). Predetermined voltages are applied to the wordline, bitline, and source of the selected cell, while the data signal (indicative of the source-to-drain current of the selected cell) is asserted to sense amplifier circuit 19. If the selected cell is in an erased state, the cell conducts a first current and the data signal indicative of this current is converted to a first voltage in circuit 19. If the selected cell is in the programmed state, it conducts a second current and the data signal indicative of this current is converted to a second voltage in circuit 19 (the "second current" flowing through a programmed cell is negligibly small when the cell is read by a typical, conventional read operation). Sense amplifier circuit 19 determines the state of the cell (i.e., whether it is programmed or erased corresponding to a binary value of 0 or 1, respectively) by comparing the voltage indicative of the cell state to a single reference voltage (supplied to circuit 19 in response to one or more control signals from controller 29). Circuit 19 asserts an output signal indicative of the outcome of this comparison (the output is either high or low, corresponding to a binary value of one or zero) to output buffer 20.
We next describe the manner in which sense amplifier circuit 19 processes a data signal from a selected target cell of array 16, with chip 3 operating as a multistate memory system (i.e., with each cell of array 16 operating as a multistate memory device). A predetermined voltage (e.g., 7 volts) is applied to the control gate of the selected cell (i.e., to the wordline of array 16 along which the selected cell is connected) while the data signal (indicative of the source-to-drain current of the selected cell) is asserted to sense amplifier circuit 19. If the selected cell is in an erased state, the cell conducts a first current and the data signal indicative of this current is converted to a first voltage in circuit 19. If the selected cell is in a first programmed state, it will conduct a different current which is converted to a second voltage in sense amplifier circuit 19. If the cell is in a second programmed state, it will conduct yet another current which is converted to a third voltage in sense amplifier circuit 19. In general, for each programmed state of the cell, the cell will conduct a distinctive current which is converted to a distinctive voltage ("VCELL") in sense amplifier circuit 19. Sense amplifier circuit 19 determines the state of the cell by comparing the voltage VCELL to each of a set of reference voltages (the reference voltages are supplied to circuit 19 in response to control signals from controller 29). Sense amplifier circuit 19 then generates encoded data (an ordered set of binary bits) indicative of the outcome of the comparisons.
We describe a case in which each cell is in one of four states (an erased state and three programmed states) with reference to FIG. 3 (which is a block diagram of a portion of an implementation of sense amplifier circuit 19). The FIG. 3 implementation of circuit 19 includes three comparator circuits (50, 51, and 52), each for comparing the voltage (VCELL) indicative of the cell state to a different reference voltage (V1, V2, or V3). Comparator 50 outputs voltage V4 which is either high or low (corresponding to a binary value of one or zero) depending on whether VCELL is less than or greater than reference voltage V1. Comparator 51 outputs voltage V5 which is either high or low (corresponding to a binary value of one or zero) depending on whether VCELL is less than or greater than reference voltage V2. Comparator 52 outputs voltage V6 which is either high or low (corresponding to a binary value of one or zero) depending on whether VCELL is less than or greater than reference voltage V3. Logic circuitry 53 receives voltage signals V4, V5, and V6, and asserts a signal E.sub.i indicative of an ordered set of two binary bits in response thereto. Circuitry 53 typically has two output lines (as indicated in FIG. 3) which assert two parallel signals determining the binary bits indicated by signal E.sub.i.
Still with reference to FIG. 3, voltage VCELL is an analog voltage signal having a magnitude in a value range, where the value range is a member of a sequence of non-overlapping value ranges L.sub.1 H.sub.1, L.sub.2 H.sub.2, L.sub.3 H.sub.3, and L.sub.4 H.sub.4. The value ranges are determined by low values L.sub.i and high values H.sub.i satisfying L.sub.1 &lt;H.sub.1 &lt;V1&lt;L.sub.2 &lt;H.sub.2 &lt;V.sub.2 &lt;L.sub.3 &lt;H.sub.3 &lt;V3&lt;L.sub.4 &lt;H.sub.4.
Each signal E.sub.i is indicative of an ordered set of two binary bits. In one example: E.sub.1 is indicative of 00; E.sub.2 is indicative of 01; E.sub.3 is indicative of 11; and E.sub.4 is indicative of 10.
In one implementation of the FIG. 1 system in which each cell of array 16 is a flash memory cell, each data signal (generated while reading one of the memory cells) received by sense amplifier circuit 19 (which includes the FIG. 3 circuit) is an analog current signal. Circuit 19 generates analog voltage signal (VCELL) from each such data signal, and the four states of each cell are defined as follows: VCELL&lt;V1; V1&lt;VCELL&lt;V2; V2&lt;VCELL&lt;V3; and V3&lt;VCELL.
More generally, when chip 3 is operating as a multistate memory system (each memory cell of which has one of three or more possible states, including an erased state), the data read from each cell cannot be represented by a single binary bit. Instead, circuit 19 outputs a signal (E'.sub.i) indicative of an ordered set of at least two binary bits, in order to represent the data read from each cell. The bits indicated by signal E'.sub.i need not be (although they can be, in special cases) identical to those indicated by above-discussed signal E.sub.i. Typically, many cells of array 16 are sequentially read (either one cell at a time, or X cells at a time, where X is a small integer such as eight), and during such a sequential read, sense amplifier circuit 19 outputs either: a signal indicative of a sequence of binary bit sets S'.sub.i, each bit set S'.sub.i consisting of binary bits read during one time period (Ti) from a cell of array 16 (where only a single cell is read at each instant); or two or more signals in parallel, each signal indicative of a sequence of binary bit sets S'.sub.ij (where multiple cells, connected along a single wordline, are read at each instant), each bit set S'.sub.ij consisting of binary bits read from a cell in a column determined by index "j" during a time period Ti determined by index "i." Each group of bit sets S'.sub.ij (for fixed value of index "i" and for all values of index "j" in a range from 1 to X) consists of X sets of data bits, each set read simultaneously from a cell in a different column (the "j"th column) of array 16. For fixed value of index "j" (and for all values of index "i" in a range from 1 to Z), each group of bit sets E'.sub.ij is a sequence of Z sets of data bits, each set read at a different time from a cell in a single column (the "j"th column) of array 16.
However, in conventional multistate memory systems such as those discussed above, the sense amplifier circuit had a fixed number (L) of input lines (each of which could be coupled to a different column of cells) and fixed number (X) of output lines. When the cells were operated as binary memory devices (each cell having two possible states), no more than the lesser of L and X of the cells could be read simultaneously. Thus, where X=2L, only L of the cells could be read simultaneously. When the cells were operated as multistate memory devices (each cell having four possible states), X=2L output lines were required to read L cells simultaneously. Undesirably, an undesirably wide output bus (consisting of X=2L output lines) was required for read a given number (e.g., L=8) of cells simultaneously. Conversely, in order to reduce the cost of implementing the system by using a relatively narrow output bus (e.g., by requiring that X not exceed 8), it was necessary to reduce system capability by restricting the number of simultaneously readable cells to an undesirably low number (e.g., L=4, where X=8) even in the case that the cells were operated as binary memory devices.
It had not been known until the present invention how to implement a multistate memory system so that desired subsets of data bits could be read from a selected cell or set of cells (of an array of flash memory cells or other memory cells), when each cell is operated as a multistate memory device. Nor had it been known until the present invention how to implement a multistate memory system so that a narrow output bus could receive all bits read simultaneously from multiple cells (connected along bitlines and wordlines) in an operating mode in which each cell operates as a multistate memory device, without degrading system capability by unduly restricting the number of cells that could be read simultaneously in an operating mode in which the cells operate as binary memory devices.